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5.2.5 AVR→FPGA

Test that all the data and the control lines are working and that the FPGA can interrupt the AVR.

The FPGA is connected to the AVR using the external SRAM interface (p. 26 in the AVR data

sheet). Reading and writing to a register in the FPGA will test all the pins (AD, ALE, RD N,

WE N). The latch and the register are implemented in the FPGA and the AVR writes and reads

this register.

Since only the lower 8 bits of the address are connected, the high bits of the address space

must be disabled by setting XMM0=XMM1=XMM2=1. The XMEM interface will be conﬁgured

to no wait-states, XMCRA=SRW10=0. The bus-keeper is enabled by setting XMBK=1.The exter-

nal memory interface is enabled by setting SRE in MCUCR.

The FPGA is memory-mapped to the addresses 0x1100-0x90FF (both inclusive). The test

program will write and read back a series of patterns (0’s, 1’s and alternating ’1’ and ’0’).

FPGA

CS is untested!!

1. Upload the test program.

2. Boot the FPGA and wait for the DONE signal.

3. Start the test program and wait for it to report success or failure.

5.2.6 FPGA→FLASH

Make sure that the connection to the on-board ﬂash is working. We don’t need to test that the

FLASH is working. The FPGA implements a simple serial interface to the ﬂash and uploads

some data and tries to read it back.

1. Try all 1’s and all 0’s, and alternating 1’s and 0’s.

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DK Digital AVR-500 Datenblatt Seite 32