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3.2.2 ModelSim

In addition to ISE it might be useful to simulate a project for debugging. For this purpose Xilinx

provides ModelSim Xilinx Edition-III free of charge

Don’t forget to select the free ”Starter” version when installing. And be sure to select VHDL

and not Verilog. The license ﬁle is then requested with a web link in the start menu.

3.3 Building a Project

Building the project can be built using the Xilinx ISE graphical environment or it can be built

using the corresponding command line tools. Either way the two methods go through the same

steps. An example make ﬁle has been provided as Appendix E.

Along with the platform two example projects have been provided: An 8051 core Oregano

and an AVR core Nimbus

3.3.1 Oregano

Oregano is an open source, freely available 8051 core

adapted to the Xilinx environment. It is

a straight forward 8051 implementation with a few external peripherals such as UART.

Boot Loading Programs

Provided with the Oregano 8051 is a boot loader example design (RAMLOAD) this program

accepts programs from the UART and stores them in the code memory space of the 8051. This

boot loader resides in the internal memory (ROM) of the 8051 and is booted as the ﬁrst program.

At start-up the boot loader emits a “=” and expects a program to be uploaded once the

upload is complete it emits a “:” and waits for a command to start executing further[1].

Send a “/2000” to start the program at address 2000

If the address is accepted it sends a “@” before jumping to the address

Uploading Programs

Building programs for oregano is the same as for any other 8051 core. Compile the program

using an 8051 compiler such as Keil PK51

and upload the program to the FPGA board using

the UART:

cat hathat.hex > /dev/ttyUSB0

echo -en "/2000\r" > /dev/ttyUSB0

http://www.xilinx.com/ise/optional prod/mxe.htm

http://www.oregano.at/

http://www.keil.com

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DK Digital AVR-500 Datenblatt Seite 18